1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the invention relates to a semiconductor device having a microstructure and a multi-layer wiring structure, and a method of fabricating the same.
2. Related Art
Multi-layer wiring structure is needed, since semiconductor devices are more highly integrated and the density of wiring lines for interconnecting elements increases. This requires an interlayer insulating film between first and second wiring layers to be made flat to prevent the disconnection of wiring lines on steps of the elements and first wiring layer. Conventionally, organic or inorganic silicon oxide coating films have been used as a flattening material, resulting in the generation of particles and cracks and the deterioration of transistor characteristics due to moisture diffusion in the film.
In recent years, a film (hereinafter referred to as "TEOS/O.sub.3 --SiO.sub.2 film") formed by way of the atmospheric pressure chemical vapor deposition (CVD) process employing O.sub.3 /tetraethyl orthosilicate (TEOS) as a source material has been attracting a great deal of attention as an interlayer film for LSIs having the micropatterns, since the TEOS/O.sub.3 --SiO.sub.2 can be formed at a low temperature below 400.degree. C. and has a selfflattening property that allows a step coverage to have a flowing shape in deposition.
The deposition rate of the TEOS/O.sub.3 --SiO.sub.2 film, however, is highly underlayer-dependent, which differs depending on materials and shapes of the underlying layer. The deposition rate is high when the underlayer is silicon and is low when the underlayer is an insulating film such as SiO.sub.2 film. Further, the deposition rate also differs depending on the flow ratio of O.sub.3 to TEOS.
In general, films deposited under a condition of high O.sub.3 /TEOS flow ratio have a higher crack-resistance, a lower moisture content in the film, and a better step coverage than those deposited under a condition of low O.sub.3 /TEOS flow ratio and provide an excellent film quality, but are disadvantageous in that they depend heavily on the underlayer. The TEOS/O.sub.3 --SiO.sub.2 film, which contains moisture, presents the problems of low reliability resulting from hot carriers and corrosion of wiring lines when used in MOS devices.
To solve the problems, Japanese Unexamined Patent Publication No. 2(1990)-209753 discloses an interlayer film of three-layer construction consisting of a plasma SiO.sub.2 film, a TEOS/O.sub.3 --SiO.sub.2 film and a plasma SiO.sub.2 film. A manufacturing process of the interlayer film is illustrated in FIGS. 6(a) to 6(c).
First, an interlayer insulating film 4 is formed over a semiconductor substrate 1 on which a gate oxide film 2 and a gate electrode 3 are formed. A first wiring layer 5 is formed on the interlayer insulating film 4, and a first silicon oxide film 7 (plasma SiO.sub.2 film) is formed so as to cover the interlayer insulating film 4 and the first wiring layer 5. Then, a TEOS/O.sub.3 --SiO.sub.2 film 8 is formed over the first silicon oxide film 7 (see FIG. 6(a)).
In turn, the TEOS/O.sub.3 --SiO.sub.2 film 8 is etched back to form a second silicon oxide film 10. A third silicon oxide film 11 (plasma SiO.sub.2 film) is formed over the second silicon oxide film 10 (see FIG. 6(b)).
The first silicon oxide film, the second silicon oxide film and the third silicon oxide film formed above the first wiring layer are subjected to an etching process to form a connecting hole therethrough. A second wiring layer is formed in the connecting hole by way of a photoresist process. Thus, a semiconductor device is fabricated (see FIG. 6(c)).
It is thought that the first silicon oxide film 7 and third silicon oxide film 11 (plasma SiO.sub.2 films) act as a barrier layer against organic substances produced when the TEOS/O.sub.3 --SiO.sub.2 film 8 is formed, and also serve to alleviate the underlayer-dependence of the TEOS/O.sub.3 --SiO.sub.2 film 8 when the first silicon oxide film 7 is 2000 .ANG. to 3000 .ANG. thick.
Japanese Unexamined Patent Publication No. 5(1993)-41459 discloses a two-layer structure consisting of a silicon nitride film formed by way of the low pressure CVD process or plasma CVD process and the TEOS/O.sub.3 --SiO.sub.2 film formed on the silicon nitride film to improve the step coverage configuration.
Japanese Unexamined Patent Publication No. 63(1988)-207168, which does not employ the TEOS/O.sub.3 --SiO.sub.2 film, discloses a three-layer structure consisting of a plasma SiN film of 200 .ANG. in thickness, a CVD SiO.sub.2 film, and an SOG (spin on glass) film to prevent moisture penetration through the plasma SiN film.
The above discussed prior art techniques present the following.
(1) Japanese Unexamined Patent Publication No. 2-209753
Where the O.sub.3 /TEOS flow ratio is low (=1), it will be understood from FIG. 2(a) that the deposition rate of the TEOS/O.sub.3 --SiO.sub.2 film on an Si wafer is generally equal to that on a flat portion (at the point A in FIG. 4) with a metal pattern, but the deposition rate of the TEOS/O.sub.3 --SiO.sub.2 film is not satisfactory. In FIG. 2(a), the open circles represent the deposition rate of the TEOS/O.sub.3 --SiO.sub.2 film on the Si wafer, and the solid circles represent the deposition rate of the TEOS/O.sub.3 --SiO.sub.2 film on the flat portion (at the point A in FIG. 4) with the metal pattern. The triangles of FIG. 2(a) represent the deposition rate on the flat portion with a metal pattern in accordance with the present invention.
Where the O.sub.3 /TEOS flow ratio is high (=7) for formation of a TEOS/O.sub.3 --SiO.sub.2 film of excellent quality, it will be understood from FIG. 2(b) that the deposition rate greatly differs between the TEOS/O.sub.3 --SiO.sub.2 film on the Si wafer and the TEOS/O.sub.3 --SiO.sub.2 film on the flat portion (at the point A in FIG. 4) with the metal pattern, failing to provide the flatness. In FIG. 2(b), the open circles represent the deposition rate of the TEOS/O.sub.3 --SiO.sub.2 film on the Si wafer, and the solid circles represent the deposition rate of the TEOS/O.sub.3 --SiO.sub.2 film on the flat portion (at the point A in FIG. 4) with the metal pattern. The low deposition rate of the TEOS/O.sub.3 --SiO.sub.2 film on the flat portion leads to decreased throughput. Further, variations in film thickness within the wafer surface cause the TEOS/O.sub.3 --SiO.sub.2 film to have different thicknesses around the point A on the wafer as shown in FIGS. 5 and 5(a), resulting in variations in thickness of the interlayer insulating film. In FIG. 5, the open circles represent the film thickness distribution on the Si wafer, and the open squares represent the film thickness distribution on the SiO.sub.2 film. It will be appreciated from FIG. 5 that the maximum film thickness on the wiring lines is about twice the minimum film thickness, and the film thickness cannot be rendered uniform.
Another problem is that moisture contained in the TEOS/O.sub.3 --SiO.sub.2 film is diffused into the gate oxide film of an underlayer transistor and field transistor by subsequent heat treatment. The moisture acting as a positively fixed charge deteriorates a resistance to hot carriers by about an order of 10 or decreases a field breakdown voltage of the field transistor.
(2) As to Japanese Unexamined Patent Publication No. 5-41459 referring to FIG. 7 of the present application, the TEOS/O.sub.3 --SiO.sub.2 film on an SiN film has a greater angle of tilt in a step portion, and accordingly is less flat than that on SiO.sub.2, failing to meet the requirements for the microstructure of devices. The data of FIG. 7 of the present disclosure is for a wiring thickness of 0.7 um, TEOS/O.sub.3 --NSG film thickness of 1.3 um, silicon nitride thickness of 500 .ANG. and a silicon oxide thickness of 1000 .ANG..
The SiN film as thin as 200 .ANG. improves surface homology. However, the thin SiN film, when used on Al wiring lines, does not function as a barrier against moisture for step coverage, and thus fails to maintain stable transistor characteristics as will be apparent from FIG. 8, in which a long relative life means a small influence of moisture in the TEOS/O.sub.3 --SiO.sub.2 film. Relative life is the ratio of hot carrier life after formation of the interlayer insulating film to hot carrier life after the first layer wiring, wherein "hot carrier life" is the time required for 10% deterioration of .beta. of a transistor.
(3) Japanese Unexamined Patent Publication No. 63-207168
A complicated wiring structure of an LSI decreases the wiring width and inevitably increases the wiring height in order to prevent an increase in the wiring resistance, resulting in an increased step. To flatten the step, it is necessary to increase the thickness of the SOG film. However, the increase in the thickness varies with the volume of the SOG film due to solvent evaporation when heated, generating cracks at the edges of the SOG film and deteriorating the film quality. Further, there arises another problem of particle generation.
The SOG film formed by way of the spin coating process is prone to cause a problem of wettability when narrow and deep gaps are coated therewith, and accordingly has not been adapted for semiconductor devices having a microstructure.
Furthermore, gases evolved from the SOG film exposed in a contact portion causes certain compounds to be formed on the surface of the wiring layer and thus increases the viahole resistance.